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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMVIDSR, VMID Sample Register</h1><p>The PMVIDSR characteristics are:</p><h2>Purpose</h2>
        <p>Contains the sampled VMID value that is captured on reading PMU.PMPCSR[31:0].</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_PMUv3_EXT32 is implemented, FEAT_PCSRv8p2 is implemented and EL2 is implemented. Otherwise, direct accesses to PMVIDSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>PMVIDSR is in the Core power domain.</p>

      
        <p>If FEAT_PMUv3_EXT64 is implemented, the same content is present in the same location, and can be accessed using PMVCIDSR[63:32].</p>

      
        <div class="note"><span class="note-header">Note</span><p>Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of <a href="ext-eddevid.html">EDDEVID</a>.PCSample.</p></div>
      <h2>Attributes</h2>
        <p>PMVIDSR is a 32-bit register.</p>
      <p>This  register is part of the <a href="pmu.html">PMU</a> block.</p><h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="16"><a href="#fieldset_0-31_16">RES0</a></td><td class="lr" colspan="8"><a href="#fieldset_0-15_8-1">VMID[15:8]</a></td><td class="lr" colspan="8"><a href="#fieldset_0-7_0">VMID</a></td></tr></tbody></table><h4 id="fieldset_0-31_16">Bits [31:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_8-1">VMID[15:8], bits [15:8]<span class="condition"><br/>When FEAT_VMID16 is implemented:
                        </span></h4><div class="field">
      <p>Extension to VMID[7:0]. For more information, see VMID[7:0].</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_8-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_0">VMID, bits [7:0]</h4><div class="field"><p>VMID sample. The VMID associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample was generated:</p>
<ul>
<li>This field is set to an <span class="arm-defined-word">UNKNOWN</span> value if any of the following apply:<ul>
<li>EL2 is disabled in the current Security state.
</li><li>The PE is executing at EL2.
</li><li>EL2 is enabled in the current Security state, the PE is executing at EL0, EL2 is using AArch64, HCR_EL2.E2H == 1, and HCR_EL2.TGE == 1.
</li></ul>

</li><li>Otherwise:<ul>
<li>If EL2 is using AArch64 and either <span class="xref">FEAT_VMID16</span> is not implemented or <a href="AArch64-vtcr_el2.html">VTCR_EL2</a>.VS is 1, this field is set to <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>.VMID.
</li><li>If EL2 is using AArch64, <span class="xref">FEAT_VMID16</span> is implemented, and <a href="AArch64-vtcr_el2.html">VTCR_EL2</a>.VS is 0, PMVIDSR.VMID[7:0] is set to <a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>.VMID[7:0] and PMVIDSR.VMID[15:8] is <span class="arm-defined-word">RES0</span>.
</li><li>If EL2 is using AArch32, this field is set to <a href="AArch32-vttbr.html">VTTBR</a>.VMID.
</li></ul>

</li></ul>
<p>Because the value written to PMVIDSR is an indirect read of the VMID value, it is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> whether PMVIDSR is set to the original or new value if PMU.PMPCSR samples:</p>
<ul>
<li>An instruction that writes to the VMID value.
</li><li>The next Context synchronization event.
</li><li>Any instruction executed between these two instructions.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing PMVIDSR</h2>
        <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> extensions to external debug might make the value of this register <span class="arm-defined-word">UNKNOWN</span>, see <span class="xref">'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'</span>.</p>
      <p>Accesses to this register use the following encodings:</p><h4 class="assembler">Accessible at offset 0x20C from PMU</h4><ul><li>When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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